Parametrizable Hybrid Stack-Register Processor as Soft Intellectual Property Module

Paper about our "SILVERBIRD" Processor Soft IP-Module, presented at the
13th Annual IEEE International ASIC/SOC Conference 2000,
Hyatt Regency Crystal City, Washington D.C., Virginia USA,
13th - 16th September 2000


Hardware/Software Co-Design usually encounters serious problems to guarantee strong real-time constraints while serving many interrupt routines. We present an enhanced register-based RISC processor, which is capable of launching every interrupt routine within two clock cycles. This processor is implemented as soft IP-Module and features a customizable instruction set, extensive parameterization, and a synthesis model with separate core and interfaces. An automatic derivation of adequate test vectors from the current parameter setting verifies the correct functionality.


In Proceedings of the 13th Annual IEEE International ASIC/SOC Conference 2000, Washington D.C., USA, pp. 87-91

Layout A4: asic_soc2000_A4.pdf   (646 kB)
Layout Letter:     asic_soc2000_letter.pdf   (646 kB)


Layout A4: presentation_A4_2.pdf   (2.4 MB)
(bright version for printing, two slides on one page)

Verification Glue: How to compose System-Level Environments

Written by Peter Lüthi and Ulrich Hensel, both AMD Dresden Design Center, Dresden, Germany
for "Verisity's Club Verification"
3rd Annual European Specman User Group Conference,
DATE03, Munich, Germany,
3rd March, 2003

Agenda of presentations at Club Verification Europe 2003


We will present a verification methodology used within AMD Dresden Design Center, Germany that evolved from a former approach based on a score board technique. This verification methodology and corresponding verification component library was applied to PC infrastructure chipset development at AMD Dresden Design Center. PC infrastructure chipset designs consist of various peripheral controllers and bridges. They share a common bus - the so-called host bus - connecting them to the processor and the memory subsystem. The majority of the peripheral controllers are complex enough to deserve a block-level verification environment. The complete system-level verification environment needs to be composed of the individual block level environments for maximum reuse. This reuse includes not only stimulus generation, but also the reuse of checkers and reference models. Aiming at these requirements, our methodology fulfills the following general goals:

  • Stimulation and checker components are independent of host bus specifics.
  • Checking is completely independent from stimulus generation.
  • Data flow and consistency check is distinguished from resource access check, i.e. the legality of memory access.
  • Both generation and checking units can be composed uniformly to build a system-level verification environment.

Our methodology is based on a library of verification components and common Specman e base units providing abstract interfaces for transactions, (bus functional) models, watchers (monitors), response generators, and transaction checkers. A so-called transaction dispatcher implements the composition schemes for response generators and transaction checkers based on these abstract interfaces. Our presentation will outline these interfaces and composition schemes using a typical chipset verification example.



Layout A4: AMD_verification_glue.pdf   (690 kB)
I received the best presentation award from the audience for this presentation.


Last updated: 15.01.2006


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